SoC Verification Engineer - Design for Debug/Design For Test
Job Details:
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Job Description:
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Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD) and Design for Test ( DFT ).
As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.
Your responsibilities will include but not be limited to:
\- Validation of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA
\- Validation of Design for Test features like TAP, SCAN and so on.
\- Knowledge on Tessent tools will be a plus
\- Development of testcases in Python for Emulation platform
\- Post-si support
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