AI SoC Modeling Engineer, Annapurna Labs Machine Learning Accelerators, AWS
Description
AWS's Trainium and Inferentia chips power the world's largest machine learning clusters. Our team builds C++ models of these custom SoCs that RTL designers, verification engineers, and software teams depend on throughout the silicon development lifecycle. We're looking for a modeling engineer to build and own models that directly impact how our chips are designed, verified, and brought to production.
What You'll Do
- Develop and maintain high-fidelity functional model of AI/ML accelerator and its SoC subsystems, including compute engines, memory hierarchies, on-chip interconnects, and data paths — translating architecture specs and RTL behavior into accurate, testable C++ models
- Validate model behavior against RTL simulations, emulation platforms, or silicon measurements; debug discrepancies and drive model-to-RTL correlation to high fidelity
- Partner with design verification teams to integrate models into pre-silicon validation environments and catch architectural bugs early in the design cycle
- Collaborate with architects/micro-architects, RTL design engineers, ML SW engineers, and compiler engineers to evaluate architecture and microarchitecture tradeoffs and help make hardware design decisions
- Contribute to cycle-approximate performance model effort enabling architectural exploration ahead of RTL availability, early software development
- Quantify system-level tradeoffs across compute, memory bandwidth, networking, and storage to influence reference architectures and long-term silicon strategy
- Build and improve modeling infrastructure: simulation frameworks, regression suites, automated correlation checks, and coverage-driven validation flows
- Develop modeling methodologies and tools that scale across multiple IP blocks and SoC generations, improving team efficiency and model reuse
Why This Role Is Interesting
- Your models are used to verify silicon before it's built — bugs you catch save months...
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