Silicon Engineering Technical Lead

The application window is expected to close on: 11/22/2026

Meet the Team

Join a team that integrates new silicon architecture, support new product development to volume production, perform manufacturing test validation, and system deployment for next-generation high-speed networking products. We work collaboratively across ASIC, optics, hardware, firmware, and manufacturing teams to deliver advanced networking solutions.

Your Impact As a Silicon Engineering Technical Lead, you will conduct root-cause analysis from system-level failures down to silicon behavior. You will develop silicon validation and characterization of functional coverage, performance, stress, corner-case, and interoperability testing. Your role involves establishing silicon performance margins and operating limits, and correlating silicon characterization data with system-level behavior. You will support manufacturing failure analysis and containment of silicon, referencing failures originating from subsystems including ASIC, SerDes, Substrate, Packaging, Thermal, Firmware/SDK, and Optics. Additionally, you will influence coverage through ATE, wafer-level, and package-level testing, while working with ASIC design teams, system architects, manufacturing operations, and network systems design.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of experience in silicon engineering, ASIC validation, or a related technical domain.
• Experience with silicon architecture and performance characterization.
• Knowledge of signal integrity and high-speed SerDes.
• Experience conducting root-cause analysis from system-level failures to silicon behavior.
• Experience with Design for Testability (DFT), scan, MBIST, LBIST, boundary scan/JTAG, and production test methodologies.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with automated test equipment (ATE), wafer-level testing, and package-level testing.
• Experience correlating silicon c...

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